Table of Contents
VLSI Design
Volume 14, Issue 4, Pages 337-347

Fast Inner Product Computation on Short Buses

1Department of Computer Science, SUNY at Geneseo, Geneseo, NY 14454, USA
2Department of Computer Science, Old Dominion University, Norfolk, VA 23529, USA

Received 3 December 2000; Revised 12 April 2001

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We propose a VLSI inner product processor architecture involving broadcasting only over short buses (containing less than 64 switches). The architecture leads to an efficient algorithm for the inner product computation. Specifically, it takes 13 broadcasts, each over less than 64 switches, plus 2 carry-save additions (tcsa) and 2 carry-lookahead additions (tcla) to compute the inner product of two arrays of N=29 elements, each consisting of m=64 bits. Using the same order of VLSI area, our algorithm runs faster than the best known fast inner product algorithm of Smith and Torng [“Design of a fast inner product processor,” Proceedings of IEEE 7th Symposium on Computer Arithmetic (1985)], which takes about 28 tcsa + tcla for the computation.