Abstract
An automatic logic/circuit synthesizer is developed which takes several Boolean functions as input and generates netlist output with basic composing cells from the pass-transistor cell library containing only two types of cells: 2-to-1 multiplexers and inverters. The synthesis procedure first constructs efficient binary decision diagrams (BDDs) for these Boolean functions considering both multi-function sharing and minimum width. Each node in the BDD trees is realized by using a 2-to-1 multiplexer (MUX) of proper driving capability designed pass-transistor logic. The inverters are then inserted all along the MUX paths in order to improve the speed performance and to alleviate the voltage-drop problem. Several methods are proposed to reduce the critical path delay in the multiplexer-chains for generation of faster circuits. Compared to the recently proposed pass-transistor-based top-down design, our synthesizer has better speed and area performance due to the reduced number of cascaded inverters.