Table of Contents
VLSI Design
Volume 14, Issue 2, Pages 183-191

A Parallel Residue-to-binary Converter for the Moduli Set {2m1,220m+1,221m+1,,22km+1}

1Department of Electrical and Computer Engineering, Centre for Signal Processing and Communications, Concordia University, 1455 de Maisonneuve Blvd. West, Montreal, Que. H3G 1M8, Canada
2Department of Computer Science, University of Texas at Dallas, Richardson, TX 75083-0688, USA

Received 13 January 2000; Revised 9 March 2000

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper, a high-speed parallel residue-to-binary converter is proposed for a recently introduced moduli set Sk={2m1,220m+1,221m+1,,22km+1} for a general value of k. The proposed converter uses simple cyclic shift and concatenation operations and does not require any multiplier. Individual converters for the cases of k=0 and k=1 are derived from the general architecture and compared with those existing in the literature. The converter for S0 is twice as fast requiring only one-half of the hardware, while that of S1 is three times as fast, but requiring only 60% of the hardware, as compared to the corresponding ones existing in the literature. Furthermore, the proposed converters are implemented using 0.5-micron CMOS VLSI technology. Based on S0 , the layouts for 8-bit, 16-bit, 32-bit and 64-bit converters are generated, and the corresponding simulation results obtained.