Table of Contents
VLSI Design
Volume 14, Issue 4, Pages 389-395

A Fast Dynamic 64-bit Comparator with Small Transistor Count

Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan

Received 1 May 2000; Revised 16 March 2001

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper, we propose a 64-bit fast dynamic CMOS comparator with small transistor count. Major features of the proposed comparator are the rearrangement and re-ordering of transistors in the evaluation block of a dynamic cell, and the insertion of a weak n feedback inverter, which helps the pull-down operation to ground. The simulation results given by pre-layout tools, e.g. HSPICE, and post-layout tools, e.g. TimeMill, reveal that the delay is around 2.5 ns while the operating clock rate reaches 100 MHz. A physical chip is fabricated to verify the correctness of our design by using UMC (United Microelectronics Company) 0.5 μm (2P2M) technology.