Table of Contents
VLSI Design
Volume 14, Issue 3, Pages 287-298

Low-power Application-specific Parallel Array Multiplier Design for DSP Applications

1Department of Electrical and Computer Engineering, State University of New York at Stony Brook, Stony Brook, NY 11794-2350, USA
2Department of Electrical Engineering and Computer Science, University of Michigan at Ann Arbor, Ann Arbor, MI 48105-2122, USA

Received 11 October 2000; Revised 14 January 2001

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • Bipin Kumar Verma, Shyam Akashe, and Sanjay Sharma, “Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier,” International Journal of Electronics, pp. 1–16, 2014. View at Publisher · View at Google Scholar
  • Pankaj Kumar, and Rajender Kumar Sharma, “Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing,” Journal of Circuits, Systems and Computers, pp. 1750030, 2016. View at Publisher · View at Google Scholar