Table of Contents
VLSI Design
Volume 15, Issue 1, Pages 455-468
http://dx.doi.org/10.1080/1065514021000012066

Low-power Implementation of an Encryption/Decryption System with Asynchronous Techniques

Electrical and Computer Engineering Department, VLSI Design Laboratory, University of Patras, Patras, Greece

Received 19 February 2001; Revised 21 June 2001

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [5 citations]

The following is the list of published articles that have cited the current article.

  • Vikash Sehwag, and Tanujay Saha, “TV-PUF: A Fast Lightweight Analog Physical Unclonable Function,” 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 182–186, . View at Publisher · View at Google Scholar
  • Pak-Keung Leung, Chiu-Sing Choy, Cheong-Fat Chan, and Kong-Pang Pun, “A low power asynchronous GF(2/sup 173/) ALU for elliptic curve crypto-processor,” Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., vol. 5, pp. V-337–V-340, . View at Publisher · View at Google Scholar
  • M. Macchetti, and Wenyu Chen, “ASIC Hardware Implementation of the IDEA NXT Encryption Algorithm,” 2006 IEEE International Symposium on Circuits and Systems, pp. 4843–4846, . View at Publisher · View at Google Scholar
  • Benfano Soewito, Lucas Vespa, and Ning Weng, “Characterizing power and resource consumption of encryption/decryption in portable devices,” 2008 IEEE Region 5 Conference, 2008. View at Publisher · View at Google Scholar
  • Niraj Kumar, Vishnu Mohan Mishra, and Adesh Kumar, “Smart grid security with AES hardware chip,” International Journal of Information Technology, 2018. View at Publisher · View at Google Scholar