Table of Contents
VLSI Design
Volume 15, Issue 3, Pages 595-604

Performance Driven Global Routing Through Gradual Refinement

1Department of EE, Texas A&M University, College Station 77843-3128, TX, USA
2Department of ECE, University of Minnesota, Minneapolis 55455, MN, USA

Received 15 March 2001; Revised 30 January 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We propose a heuristic for VLSI interconnect global routing that can optimize routing congestion, delay and number of bends, which are often competing objectives. Routing flexibilities under timing constraints are obtained and exploited to reduce congestion subject to timing constraints. The wire routes are determined through gradual refinement according to probabilistic estimation on congestions so that the congestion is minimized while the number of bends on wires is limited. The experiments on both random generated circuits and benchmark circuits confirm the effectiveness of this method.