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VLSI Design
Volume 14 (2002), Issue 4, Pages 363-372

Word-serial Architectures for Filtering and Variable Rate Decimation

Wireless Integrated Systems Laboratory, Electrical Engineering Department, 56-425B Eng. IV Bldg., UCLA, Los Angeles 90095-1594, CA, USA

Received 1 May 2000; Revised 2 January 2001

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A new flexible architecture is proposed for word-serial filtering and variable rate decimation/interpolation. The architecture is targeted for low power applications requiring medium to low data rate and is ideally suited for implementation on either an ASIC or an FPGA. It combines the small size and low power of an ASIC with the programmability and flexibility of a DSP. An efficient memory addressing scheme eliminates the need for power hungry shift registers and allows full reconfiguration. The decimation ratio, filter length and filter coefficients can all be changed in real time. The architecture takes advantage of coefficient symmetries in linear phase filters and in polyphase components.