VLSI Design

VLSI Design / 2002 / Article

Open Access

Volume 15 |Article ID 906534 | https://doi.org/10.1080/1065514021000012011

Shyue-Kung Lu, Fu-Min Yeh, Jen-Sheng Shih, "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs", VLSI Design, vol. 15, Article ID 906534, 10 pages, 2002. https://doi.org/10.1080/1065514021000012011

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs

Received28 Feb 2001
Revised23 May 2001


In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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