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VLSI Design
Volume 15, Issue 1, Pages 397-406
http://dx.doi.org/10.1080/1065514021000012011

Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs

1Department of Electronic Engineering, Fu Jen Catholic University, Taipei, Taiwan
2Electronics Systems Division, Chung-Shan Institute of Science and Technology, Taipei, Taiwan

Received 28 February 2001; Revised 23 May 2001

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [8 citations]

The following is the list of published articles that have cited the current article.

  • Niamat, Santhanam, and Kim, “JHDL implementation of a BIST scheme for testing the look-up tables of SRAM based FPGAs,” Midwest Symposium on Circuits and Systems, vol. 2, pp. 327–331, 2006. View at Publisher · View at Google Scholar
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