Table of Contents
VLSI Design
Volume 14, Issue 1, Pages 107-122

Term Trees in Application to an Effective and Efficient ATPG for AND–EXOR and AND–OR Circuits

1Faculty of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513 EH 10.25, Eindhoven 5600, MB, The Netherlands
2Department of Electrical and Computer Engineering, Portland State University, Portland 97207, OR, USA

Received 20 January 2000; Revised 4 October 2000

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Petr Fiser, Premysl Rucky, and Irena Vanova, “Fast Boolean minimizer for completely specified functions,” Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, pp. 122–127, 2008. View at Publisher · View at Google Scholar
  • Petr Fiser, and David Tomanpp. 757–764, 2009. View at Publisher · View at Google Scholar
  • Lech Jozwiak, Nadia Nedjah, and Miguel Figueroa, “Modern development methods and tools for embedded reconfigurable systems: A survey,” Integration-The Vlsi Journal, vol. 43, no. 1, pp. 1–33, 2010. View at Publisher · View at Google Scholar