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VLSI Design
Volume 2007, Article ID 37627, 11 pages
Research Article

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

1Computer Systems Lab, Stanford University, Stanford, CA 94305-9040, USA
2Departamento Arquitectura de Computadores y Automatica, Universidad Complutense de Madrid, Madrid 28040, Spain
3Laboratoire des Systèmes Intégrés, Ecole Polytechnique Federale de Laussanne, Lausanne 1015, Switzerland
4Dipartimento di Elettronica, Informatica e Sistemistica, Università di Bologna, Bologna 40126, Italy

Received 16 October 2006; Revised 21 January 2007; Accepted 6 February 2007

Academic Editor: Maurizio Palesi

Copyright © 2007 Srinivasan Murali et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today's NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power consumption. Multiple paths can also be utilized to achieve spatial redundancy, which helps in achieving tolerance against faults or errors in the NoC. A major problem with multipath routing is that packets can reach the destination in an out-of-order fashion, while many applications require in-order packet delivery. In this work, we present a multipath routing strategy that guarantees in-order packet delivery for NoCs. It is based on the idea of routing packets on partially nonintersecting paths and rebuilding packet order at path reconvergent nodes. We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network bandwidth needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large reduction in network bandwidth requirements (36.86% on average) and power consumption (30.51% on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5% increase in network area). Hence, it is practical to be used in the on-chip domain.