Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2007 (2007), Article ID 37627, 11 pages
http://dx.doi.org/10.1155/2007/37627
Research Article

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

1Computer Systems Lab, Stanford University, Stanford, CA 94305-9040, USA
2Departamento Arquitectura de Computadores y Automatica, Universidad Complutense de Madrid, Madrid 28040, Spain
3Laboratoire des Systèmes Intégrés, Ecole Polytechnique Federale de Laussanne, Lausanne 1015, Switzerland
4Dipartimento di Elettronica, Informatica e Sistemistica, Università di Bologna, Bologna 40126, Italy

Received 16 October 2006; Revised 21 January 2007; Accepted 6 February 2007

Academic Editor: Maurizio Palesi

Copyright © 2007 Srinivasan Murali et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [19 citations]

The following is the list of published articles that have cited the current article.

  • Radu Marculescu, and Paul Bogdan, “The Chip is the network: Toward a science of network-on-chip design,” Foundations and Trends in Electronic Design Automation, vol. 2, no. 4, pp. 371–461, 2007. View at Publisher · View at Google Scholar
  • Myong Hyon Cho, Chih-Chi Cheng, Michel Kinsy, G. Edward Suh, and Srinivas Devadas, “Diastolic arrays: Throughput-driven reconfigurable computing,” IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, pp. 457–464, 2008. View at Publisher · View at Google Scholar
  • Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, Natalie Enright Jerger, and Yatin Hoskote, “Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3–21, 2009. View at Publisher · View at Google Scholar
  • Michel Kinsy, Myong Hyon Cho, Tina Wen, Edward Suh, Marten Van Dijk, and Srinivas Devadas, “Application-aware deadlock-free oblivious routing,” Proceedings - International Symposium on Computer Architecture, pp. 208–219, 2009. View at Publisher · View at Google Scholar
  • Qiaoyan Yu, and Paul Ampadu, “Dual-layer cooperative error control for reliable nanoscale networks-on-chip,” Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 431–439, 2009. View at Publisher · View at Google Scholar
  • Yonghui Li, and Huaxi Gu, “Fault tolerant routing algorithm based on the artificial potential field model in Network-on-Chip,” Applied Mathematics And Computation, vol. 217, no. 7, pp. 3226–3235, 2010. View at Publisher · View at Google Scholar
  • Girish Vishnu Varatkar, Sriram Narayanan, Naresh R. Shanbhag, and Douglas L. Jones, “Stochastic Networked Computation,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 10, pp. 1421–1432, 2010. View at Publisher · View at Google Scholar
  • Mohamed M. Sabry, Martino Ruggiero, and Pablo G. Del Valle, “Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs,” Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, pp. 305–310, 2010. View at Publisher · View at Google Scholar
  • Majed Chatti, Sami Yehia, Claude Timsit, and Soraya Zertal, “A hypercube-based NoC routing algorithm for efficient all-to-all communications in embedded image and signal processing applications,” Proceedings of the 2010 International Conference on High Performance Computing and Simulation, HPCS 2010, pp. 623–630, 2010. View at Publisher · View at Google Scholar
  • R. Stefan, and K. Goossens, “A TDM slot allocation flow based on multipath routing in NoCs,” Microprocessors and Microsystems, vol. 35, no. 2, pp. 130–138, 2011. View at Publisher · View at Google Scholar
  • Radu Stefan, and Kees Goossens, “Multi-path routing in time-division-multiplexed networks on chip,” Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, pp. 109–114, 2011. View at Publisher · View at Google Scholar
  • Alzemiro H. Lucas, and Fernando G. Moraes, “Crosstalk fault tolerant NoC - Design and evaluation,” Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, pp. 115–120, 2011. View at Publisher · View at Google Scholar
  • K. Somasundaram, and Juha Plosila, “Deadlock Free Routing Algorithm for Minimizing Data Packet Transmission in Network on Chip,” International Journal of Embedded and Real-Time Communication Systems, vol. 3, no. 1, pp. 70–81, 2012. View at Publisher · View at Google Scholar
  • Michel A. Kinsy, Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, G. Edward Suh, and Srinivas Devadas, “Optimal and Heuristic Application-Aware Oblivious Routing,” Ieee Transactions On Computers, vol. 62, no. 1, pp. 59–73, 2013. View at Publisher · View at Google Scholar
  • Ved Prakash Bhardwaj, and Nitin, “Message Broadcasting via a New Fault Tolerant Irregular Advance Omega Network in Faulty and Nonfaulty Network Environments,” Journal of Electrical and Computer Engineering, vol. 2013, pp. 1–16, 2013. View at Publisher · View at Google Scholar
  • Faizal Arya Samman, Thomas Hollstein, and Manfred Glesner, “Runtime contention and bandwidth-aware adaptive routing selection strategies for networks-on-chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 24, no. 7, pp. 1411–1421, 2013. View at Publisher · View at Google Scholar
  • K. Somasundaram, Juha Plosila, and N. Viswanathan, “Deadlock free routing algorithm for minimizing congestion in a Hamiltonian connected recursive 3D-NoCs,” Microelectronics Journal, vol. 45, no. 8, pp. 989–1000, 2014. View at Publisher · View at Google Scholar
  • Masoud Daneshtalab, Masoumeh Ebrahimi, Sergei Dytckov, and Juha Plosila, “In-order delivery approach for 2D and 3D NoCs,” The Journal of Supercomputing, 2014. View at Publisher · View at Google Scholar
  • Farhad Pakdaman, Abbas Mazloumi, and Mehdi Modarressi, “Integrated circuit-packet switching NoC with efficient circuit setup mechanism,” Journal of Supercomputing, vol. 71, no. 8, pp. 2787–2807, 2015. View at Publisher · View at Google Scholar