Power Consumption and BER of Flip-Flop Inserted Global Interconnect

Xu, Jingye; Roy, Abinash; Chowdhury, Masud H.

doi:https://doi.org/10.1155/2007/42829

VLSI Design

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Research Article | Open Access

Volume 2007 | Article ID 042829 | https://doi.org/10.1155/2007/42829

Power Consumption and BER of Flip-Flop Inserted Global Interconnect

Jingye Xu,¹Abinash Roy,¹and Masud H. Chowdhury¹

Academic Editor: Bernard Courtois

Received23 Oct 2006

Revised14 Mar 2007

Accepted02 Apr 2007

Published21 Jun 2007

Abstract

In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential elements into the global interconnect lines has been proposed to support multicycle communication—a concept known as interconnect pipelining. The design targets of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and less delay cycles. This paper presents an in-depth analysis of the reliability in terms of bit error rate (BER) and the power consumption of wire-pipelining scheme. In this analysis, the dependencies of power consumption and BER on the number of inserted flip-flops, and the size of repeaters are illustrated. To trade off the design targets (wire delay, BER, and power consumption), a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit. The methodology is demonstrated by calculating optimal solutions for interconnect pipelining for some International Technology Roadmap for Semiconductor technology nodes.

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Copyright

Copyright © 2007 Jingye Xu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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