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VLSI Design
Volume 2007 (2007), Article ID 50285, 12 pages
http://dx.doi.org/10.1155/2007/50285
Research Article

Area and Power Modeling for Networks-on-Chip with Layout Awareness

1Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy
2Department of Electronics and Information Scince (DEIS), University of Bologna, Bologna 40136, Italy
3Department of Mathematics and Information Science, University of Cagliari, Cagliari 09123, Italy

Received 1 November 2006; Revised 2 February 2007; Accepted 1 March 2007

Academic Editor: Maurizio Palesi

Copyright © 2007 Paolo Meloni et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [12 citations]

The following is the list of published articles that have cited the current article.

  • Seung Eun Lee, and Nader Bagherzadeh, “A high level power model for Network-on-Chip (NoC) router,” Computers and Electrical Engineering, vol. 35, no. 6, pp. 837–845, 2009. View at Publisher · View at Google Scholar
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  • Paolo Meloni, Simone Secchi, and Luigi Raffo, “An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures,” IEEE Embedded Systems Letters, vol. 2, no. 1, pp. 5–9, 2010. View at Publisher · View at Google Scholar
  • Maurizio Martina, and Guido Masera, “Turbo NOC: A framework for the design of network-on-chip-based turbo decoder architectures,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 10, pp. 2776–2789, 2010. View at Publisher · View at Google Scholar
  • Andrew B. Kahng, Bill Lin, and Kambiz Samadi, “Improved on-chip router analytical power and area modeling,” Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 241–246, 2010. View at Publisher · View at Google Scholar
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  • Emanuele Cannella, Lorenzo Di Gregorio, Leandro Fiorin, Menno Lindwer, Paolo Melonr, Olaf Neugebauer, and Andy Pimentel, “Towards an ESL design framework for adaptive and fault-tolerant MPSoCs: MADNESS or not?,” 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, ESTIMedia 2011, pp. 120–129, 2011. View at Publisher · View at Google Scholar
  • Maurizio Martina, and Guido Masera, “Improving Network-on-Chip-based Turbo Decoder Architectures,” Journal of Signal Processing Systems, 2013. View at Publisher · View at Google Scholar
  • Mahdieh Nadi Senejani, Mahdiar Ghadiry, Chia Yee Ooi, and Muhammad Nadzir Marsono, “Built-in Self Test Power and Test Time Analysis in On-chip Networks,” Circuits, Systems, and Signal Processing, 2014. View at Publisher · View at Google Scholar
  • Farnaz Fotovatikhah, Bahareh Naraghi, Fatemeh Tavakoli, and Mahdiar Ghadiry, “A New Approach to Model the Effect of Topology on Testing Using Boundary Scan,” Journal of Electronic Testing: Theory and Applications (JETTA), vol. 31, no. 3, pp. 301–310, 2015. View at Publisher · View at Google Scholar
  • Carlo Sau, Nicola Carta, Luigi Raffo, and Francesca Palumbo, “Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design,” Journal of Signal Processing Systems, 2015. View at Publisher · View at Google Scholar
  • Francesca Palumbo, Carlo Sau, and Luigi Raffo, “Coarse-grained reconfiguration: dataflow-based power management,” Iet Computers And Digital Techniques, vol. 9, no. 1, pp. 36–48, 2015. View at Publisher · View at Google Scholar