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VLSI Design
Volume 2007, Article ID 50285, 12 pages
http://dx.doi.org/10.1155/2007/50285
Research Article

Area and Power Modeling for Networks-on-Chip with Layout Awareness

1Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari 09123, Italy
2Department of Electronics and Information Scince (DEIS), University of Bologna, Bologna 40136, Italy
3Department of Mathematics and Information Science, University of Cagliari, Cagliari 09123, Italy

Received 1 November 2006; Revised 2 February 2007; Accepted 1 March 2007

Academic Editor: Maurizio Palesi

Copyright © 2007 Paolo Meloni et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [23 citations]

The following is the list of published articles that have cited the current article.

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