A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

Abstract

One of the key steps in Network-on-Chip-based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problems first map cores onto a topology and then route communication, using separate and possibly conflicting objective functions. In this paper, we present a unified single-objective algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+). As the main contribution, we show how to couple path selection, mapping of cores, and channel time-slot allocation to minimize the network required to meet the constraints of the application. The time-complexity of UMARS+ is low and experimental results indicate a run-time only 20% higher than that of path selection alone. We apply the algorithm to an MPEG decoder System-on-Chip, reducing area by 33%, power dissipation by 35%, and worst-case latency by a factor four over a traditional waterfall approach.

References

1. L. Benini and G. de Micheli, “Networks on chips: a new SoC paradigm,” Computer, vol. 35, no. 1, pp. 70–78, 2002. View at: Publisher Site | Google Scholar
2. M. Sgroi, M. Sheets, and A. Mihal et al., “Addressing the system-on-a-chip interconnect woes through communication-based design,” in Proceedings of the 38th Design Automation Conference (DAC '01), pp. 667–672, Las Vegas, Nev, USA, June 2001. View at: Google Scholar
3. D. Bertozzi, A. Jalabert, and S. Murali et al., “NoC synthesis flow for customized domain specific multiprocessor systems-on-chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113–129, 2005. View at: Publisher Site | Google Scholar
4. W. J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks,” in Proceedings of the 38th Design Automation Conference (DAC '01), pp. 684–689, Las Vegas, Nev, USA, June 2001. View at: Google Scholar
5. K. Goossens, J. Dielissen, O. P. Gangwal, S. Gonzàlez Pestana, A. Rădulescu, and E. Rijpkema, “A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification,” in Proceedings of Design, Automation and Test in Europe Conference and Exposition (DATE '05), pp. 1182–1187, Munich, Germany, March 2005. View at: Publisher Site | Google Scholar
6. E. Rijpkema, K. Goossens, and A. Rădulescu et al., “Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip,” IEE Proceedings: Computers and Digital Techniques, vol. 150, no. 5, pp. 294–302, 2003. View at: Publisher Site | Google Scholar
7. K. Keutzer, S. Malik, J. M. Rabaey, and A. Sangiovanni-Vincentelli, “System-level design: orthogonalization of concerns and platform-based design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1523–1543, 2000. View at: Publisher Site | Google Scholar
8. J. Hu and R. Marculescu, “Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures,” in Proceedings of Design, Automation and Test in Europe Conference and Exposition (DATE '03), pp. 688–693, Munich, Germany, March 2003. View at: Google Scholar
9. U. Y. Ogras, J. Hu, and R. Marculescu, “Key research problems in NoC design: a holistic perspective,” in Proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '05), pp. 69–74, Jersey City, NJ, USA, September 2005. View at: Google Scholar
10. M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, “Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '04), vol. 2, pp. 890–895, Paris, France, February 2004. View at: Publisher Site | Google Scholar
11. A. Laffely, J. Liang, R. Tessier, and W. Burleson, “Adaptive system on a chip (aSoC): a backbone for power-aware signal processing cores,” in Proceedings of International Conference on Image Processing (ICIP '03), vol. 3, pp. 105–108, Barcelona, Spain, September 2003. View at: Publisher Site | Google Scholar
12. R. A. Guerin, A. Orda, and D. Williams, “QoS routing mechanisms and OSPF extensions,” in Proceedings of the IEEE Global Telecommunications Conference (GLOBECOM '97), vol. 3, pp. 1903–1908, Phoenix, Ariz, USA, November 1997. View at: Publisher Site | Google Scholar
13. R. Widyono, “The design and evaluation of routing algorithms for real-time channels,” TR-94-024, International Computer Science Institute & University of California, Berkeley, Calif, USA, June 1994. View at: Google Scholar
14. I. Matta and A. Bestavros, “A load profiling approach to routing guaranteed bandwidth flows,” in Proceedings of the 17th Annual Joint Conference of the IEEE Computer and Communications Societies (INFOCOM '98), vol. 3, pp. 1014–1021, San Francisco, Calif, USA, March-April 1998. View at: Publisher Site | Google Scholar
15. R. A. Guerin and A. Orda, “Networks with advance reservations: the routing perspective,” in Proceedings of the 19th Annual Joint Conference of the IEEE Computer and Communications Societies (INFOCOM '00), vol. 1, pp. 118–127, Tel Aviv, Israel, March 2000. View at: Publisher Site | Google Scholar
16. W. H. Ho and T. M. Pinkston, “A methodology for designing efficient on-chip interconnects on well-behaved communication patterns,” in Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA '03), pp. 377–388, Anaheim, Calif, USA, February 2003. View at: Publisher Site | Google Scholar
17. S. Stuijk, T. Basten, M. Geilen, A. H. Ghamarian, and B. Theelen, “Resource-efficient routing and scheduling of time-constrained network-on-chip communication,” in Proceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD '06), pp. 45–52, Dubrovnik, Croatia, August-September 2006. View at: Publisher Site | Google Scholar
18. J. Hu and R. Marculescu, “Energy-aware mapping for tile-based NoC architectures under performance constraints,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '03), pp. 233–239, Kitakyushu, Japan, January 2003. View at: Publisher Site | Google Scholar
19. S. Murali and G. de Micheli, “Bandwidth-constrained mapping of cores onto NoC architectures,” in Proceedings of Design, Automation and Test in Europe Conference and Exposition (DATE '04), vol. 2, pp. 896–901, Paris, France, February 2004. View at: Publisher Site | Google Scholar
20. S. Murali and G. de Micheli, “SUNMAP: a tool for automatic topology selection and generation for NoCs,” in Proceedings of the 41st Design Automation Conference (DAC '04), pp. 914–919, San Diego, Calif, USA, June 2004. View at: Google Scholar
21. S. Murali, L. Benini, and G. de Micheli, “Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees,” in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC '05), vol. 1, pp. 27–32, Shanghai, China, January 2005. View at: Publisher Site | Google Scholar
22. P. M. Pardalos, F. Rendl, and H. Wolkowicz, “The quadratic assignment problem: a survey and recent developments,” in Quadratic Assignment and Related Problems, P. M. Pardalos and H. Wolkowicz, Eds., vol. 16 of DIMACS Series in Discrete Mathematics and Theoretical Computer Science, pp. 1–42, American Mathematical Society, Providence, RI, USA, 1994. View at: Google Scholar
23. L. M. Ni and P. K. McKinley, “A survey of wormhole routing techniques in direct networks,” Computer, vol. 26, no. 2, pp. 62–76, 1993. View at: Publisher Site | Google Scholar
24. C. J. Glass and L. M. Ni, “The turn model for adaptive routing,” Journal of the ACM, vol. 41, no. 5, pp. 874–902, 1994. View at: Publisher Site | Google Scholar
25. G.-M. Chiu, “The odd-even turn model for adaptive routing,” IEEE Transactions on Parallel and Distributed Systems, vol. 11, no. 7, pp. 729–738, 2000. View at: Publisher Site | Google Scholar
26. J. Hu and R. Marculescu, “DyAD: smart routing for networks-on-chip,” in Proceedings of the 41st Design Automation Conference (DAC '04), pp. 260–263, San Diego, Calif, USA, June 2004. View at: Google Scholar
27. L. Benini, “Application specific NoC design,” in Proceedings of Design, Automation and Test in Europe Conference and Exposition (DATE '06), pp. 491–495, Munich, Germany, March 2006. View at: Google Scholar
28. D. Starobinski, M. Karpovsky, and L. A. Zakrevski, “Application of network calculus to general topologies using turn-prohibition,” IEEE/ACM Transactions on Networking, vol. 11, no. 3, pp. 411–421, 2003. View at: Publisher Site | Google Scholar
29. A. Hansson, K. Goossens, and A. Rădulescu, “A unified approach to constrained mapping and routing on network-on-chip architectures,” in Proceedings of 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '05), pp. 75–80, Jersey City, NJ, USA, September 2005. View at: Google Scholar
30. S. J. Krolikoski, F. Schirrmeister, B. Salefski, J. Rowson, and G. Martin, “Methodology and technology for virtual component driven hardware/software co-design on the system-level,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '99), vol. 6, pp. 456–459, Orlando, Fla, USA, May-June 1999. View at: Google Scholar
31. I. Stoica, “Stateless core: a scalable approach for quality of service in the Internet,” Ph.D. dissertation, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pa, USA, December 2000, also as Tech. Rep. CMU-CS-00-176. View at: Google Scholar
32. H. Zhang, “Service disciplines for guaranteed performance service in packet-switching networks,” Proceedings of the IEEE, vol. 83, no. 10, pp. 1374–1396, 1995. View at: Publisher Site | Google Scholar
33. C. M. Aras, J. F. Kurose, D. S. Reeves, and H. Schulzrinne, “Real-time communication in packet-switched networks,” Proceedings of the IEEE, vol. 82, no. 1, pp. 122–139, 1994. View at: Publisher Site | Google Scholar
34. U. Y. Ogras and R. Marculescu, “Application-specific network-on-chip architecture customization via long-range link insertion,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '05), pp. 246–253, San Jose, Calif, USA, November 2005. View at: Publisher Site | Google Scholar
35. K. Srinivasan and K. S. Chatha, “A low complexity heuristic for design of custom network-on-chip architectures,” in Proceedings of Design, Automation and Test in Europe Conference and Exposition (DATE '06), pp. 130–135, Munich, Germany, March 2006. View at: Google Scholar
36. J. Xu, W. Wolf, J. Henkel, and S. Chakradhar, “A design methodology for application-specific networks-on-chip,” ACM Transactions on Embedded Computing Systems, vol. 5, no. 2, pp. 263–280, 2006. View at: Publisher Site | Google Scholar
37. W. J. Dally and C. L. Seitz, “Deadlock-free message routing in multiprocessor interconnection networks,” IEEE Transactions on Computers, vol. 36, no. 5, pp. 547–553, 1987. View at: Google Scholar
38. P. Mohapatra, “Wormhole routing techniques for directly connected multicomputer systems,” ACM Computing Surveys, vol. 30, no. 3, pp. 374–410, 1998. View at: Publisher Site | Google Scholar
39. D. H. Linder and J. C. Harden, “An adaptive and fault tolerant wormhole routing strategy for k-ary n-cubes,” IEEE Transactions on Computers, vol. 40, no. 1, pp. 2–12, 1991. View at: Publisher Site | Google Scholar | MathSciNet
40. J. Rexford and K. G. Shin, “Support for multiple classes of traffic in multicomputer routers,” in Proceedings of the 1st International Workshop on Parallel Computer Routing and Communication (PCRCW '94), pp. 116–130, Seattle, Wash, USA, May 1994. View at: Google Scholar
41. N. W. McKeown, “Scheduling algorithms for input-queued cell switches,” Ph.D. dissertation, University of California, Berkeley, Calif, USA, May 1995. View at: Google Scholar
42. W. J. Dally, “Virtual-channel flow control,” IEEE Transactions on Parallel and Distributed Systems, vol. 3, no. 2, pp. 194–205, 1992. View at: Publisher Site | Google Scholar
43. E. Fleury and P. Fraigniaud, “A general theory for deadlock avoidance in wormhole-routed networks,” IEEE Transactions on Parallel and Distributed Systems, vol. 9, no. 7, pp. 626–638, 1998. View at: Publisher Site | Google Scholar
44. T. Bjerregaard and J. Sparsø, “A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip,” in Proceedings of Design, Automation and Test in Europe Conference and Exposition (DATE '05), vol. 2, pp. 1226–1231, Munich, Germany, March 2005. View at: Publisher Site | Google Scholar
45. P. Guerrier, “Un réseau d'interconnexion pour systémes intégrés,” Ph.D. dissertation, Université Paris VI, Paris, France, 2000. View at: Google Scholar
46. I. Saastamoinen, M. Alho, and J. Nurmi, “Buffer implementation for Proteo networks-on-chip,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '03), vol. 2, pp. 113–116, Bangkok, Thailand, May 2003. View at: Google Scholar
47. C. J. Glass and L. M. Ni, “The turn model for adaptive routing,” in Proceedings of the 19th International Symposium on Computer Architecture (ISCA '92), pp. 278–287, Gold Coast, Queensland, Australia, May 1992. View at: Google Scholar
48. O. P. Gangwal, A. Rădulescu, K. Goossens, S. Gonzàlez Pestana, and E. Rijpkema, “Building predictable systems on chip: an analysis of guaranteed communication in the Æthereal network on chip,” in Dynamic and Robust Streaming in and between Connected Consumer-Electronics Devices, Kluwer Academic Publishers, Dordrecht, The Netherlands, 2005. View at: Google Scholar
49. K. Kar, M. Kodialam, and T. V. Lakshman, “Minimum interference routing of bandwidth guaranteed tunnels with MPLS traffic engineering applications,” IEEE Journal on Selected Areas in Communications, vol. 18, no. 12, pp. 2566–2579, 2000. View at: Publisher Site | Google Scholar
50. M. Fidler and G. Einhoff, “Routing in turn-prohibition based feed-forward networks,” in Proceedings of the 3rd IFIP-TC6 Networking Conference (Networking '04), vol. 3042 of Lecture Notes in Computer Science, pp. 1168–1179, Athens, Greece, May 2004. View at: Google Scholar
51. G. Liu and K. G. Ramakrishnan, “A ${}^{\ast }\text{P}\text{rune}$: an algorithm for finding $K$ shortest paths subject to multiple constraints,” in Proceedings of the 20th Annual Joint Conference of the IEEE Computer and Communications Societies (INFOCOM '01), vol. 2, pp. 743–749, Anchorage, Alaska, USA, April 2001. View at: Google Scholar
52. K. Kowalik and M. Collier, “Should QoS routing algorithms prefer shortest paths?,” in Proceedings of IEEE International Conference on Communications (ICC '03), vol. 1, pp. 213–217, Anchorage, Alaska, USA, May 2003. View at: Publisher Site | Google Scholar
53. Q. Ma and P. Steenkiste, “On path selection for traffic with bandwidth guarantees,” in Proceedings of the International Conference on Network Protocols (ICNP '97), pp. 191–202, Atlanta, Ga, USA, October 1997. View at: Publisher Site | Google Scholar
54. S. Gonzàlez Pestana, E. Rijpkema, A. Rădulescu, K. Goossens, and O. P. Gangwal, “Cost-performance trade-offs in networks on chip: a simulation-based approach,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '04), vol. 2, pp. 764–769, Paris, France, February 2004. View at: Publisher Site | Google Scholar
55. J. Dielissen, A. Rădulescu, and K. Goossens, “Power measurements and analysis of a network-on-chip,” Tech. Rep. NL-TN-2005-0282, Philips Research Laboratories, Eindhoven, The Netherlands, 2005. View at: Google Scholar

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Copyright © 2007 Andreas Hansson et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.