Abstract

An experimental filter was designed to operate at 3.6 GHz using mainstream 0.18 μm CMOS. In the design, the Q-enhancement technique was used to overcome the low-Q characteristics of the CMOS on-chip inductors. A sixth-order bandpass filter with a wide passband and a high image rejection was built by cascading three stages of second-order Q-enhanced filters. A combination of three biquads with offset in center frequency provides wider tuning frequency and bandwidth. This high-performance filter provides a 340 MHz tunable center frequency around 3.6 GHz, an image rejection of 50 dB and a tunable Q from 25 to 50 for a bandwidth adjustment from 95 MHz to 35   MHz. The filter achieves an 18 dB voltage gain while consuming 130 mW of power at 1.8 V DC supply. The chip occupies an area of 900×900μm2 including all the required bonding pads. The design provides a simple architecture to simplify tuning scheme for both frequency and bandwidth for practical use. The tunable ability of the design could be exploited in further study to be used as a channel-select filter in the gigahertz range.