VLSI Design

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Volume 2007 |Article ID 094676 | https://doi.org/10.1155/2007/94676

Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, "Online Reconfigurable Self-Timed Links for Fault Tolerant NoC", VLSI Design, vol. 2007, Article ID 094676, 13 pages, 2007. https://doi.org/10.1155/2007/94676

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

Academic Editor: Davide Bertozzi
Received15 Oct 2006
Accepted04 Mar 2007
Published07 May 2007


We propose link structures for NoC that have properties for tolerating efficiently transient, intermittent, and permanent errors. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. The protection against transient errors is realized using Hamming coding and interleaving for error detection and retransmission as the recovery method. We introduce two approaches for tackling the intermittent and permanent errors. In the first approach, spare wires are introduced together with reconfiguration circuitry. The other approach uses time redundancy, the transmission is split into two parts, where the data is doubled. In both structures the presence of permanent or intermittent errors is monitored by analyzing previous error syndromes. The links are based on self-timed signaling in which the handshake signals are protected using triple modular redundancy. We present the structures, operation, and designs for the different components of the links. The fault tolerance properties are analyzed using a fault model containing temporary, intermittent, and permanent faults that occur both as bursts and as single faults. The results show a considerable enhancement in the fault tolerance at the cost of performance and area, and with only a slight increase in power consumption.


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Copyright © 2007 Teijo Lehtonen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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