VLSI Design

VLSI Design / 2007 / Article
Special Issue


View this Special Issue

Research Article | Open Access

Volume 2007 |Article ID 094676 | https://doi.org/10.1155/2007/94676

Teijo Lehtonen, Pasi Liljeberg, Juha Plosila, "Online Reconfigurable Self-Timed Links for Fault Tolerant NoC", VLSI Design, vol. 2007, Article ID 094676, 13 pages, 2007. https://doi.org/10.1155/2007/94676

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

Academic Editor: Davide Bertozzi
Received15 Oct 2006
Accepted04 Mar 2007
Published07 May 2007


We propose link structures for NoC that have properties for tolerating efficiently transient, intermittent, and permanent errors. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. The protection against transient errors is realized using Hamming coding and interleaving for error detection and retransmission as the recovery method. We introduce two approaches for tackling the intermittent and permanent errors. In the first approach, spare wires are introduced together with reconfiguration circuitry. The other approach uses time redundancy, the transmission is split into two parts, where the data is doubled. In both structures the presence of permanent or intermittent errors is monitored by analyzing previous error syndromes. The links are based on self-timed signaling in which the handshake signals are protected using triple modular redundancy. We present the structures, operation, and designs for the different components of the links. The fault tolerance properties are analyzed using a fault model containing temporary, intermittent, and permanent faults that occur both as bursts and as single faults. The results show a considerable enhancement in the fault tolerance at the cost of performance and area, and with only a slight increase in power consumption.


  1. C. Constantinescu, “Trends and challenges in VLSI circuit reliability,” IEEE Micro, vol. 23, no. 4, pp. 14–19, 2003. View at: Publisher Site | Google Scholar
  2. International Technology Roadmap for Semiconductors, 2005, http://public.itrs.net/.
  3. T. Lehtonen, J. Plosila, and J. Isoaho, “On fault tolerance techniques towards nanoscale circuits and systems,” Tech. Rep. 708, Turku Centre for Computer Science (TUCS), Turku, Finland, August 2005. View at: Google Scholar
  4. G. De Micheli and L. Benini, Networks on Chips, Morgan Kaufmann Publishers, San Francisco, Calif, USA, 2006.
  5. D. M. Chapiro, Globally-asynchronous locally-synchronous systems, M.S. thesis, Stanford University, Stanford, Calif, USA, October 1984.
  6. P. Liljeberg, J. Plosila, and J. Isoaho, “Self-timed communication platform for implementing high-performance systems-on-chip,” Integration, the VLSI Journal, vol. 38, no. 1, pp. 43–67, 2004. View at: Publisher Site | Google Scholar
  7. J. Muttersbach, T. Villiger, and W. Fichtner, “Practical design of globally-asynchronous locally-synchronous systems,” in Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '00), pp. 52–59, Eilat, Israel, April 2000. View at: Google Scholar
  8. M. Renaudin, “Asynchronous circuits and systems: a promising design alternative,” Microelectronic Engineering, vol. 54, no. 1-2, pp. 133–149, 2000. View at: Google Scholar
  9. C. L. Seitz, “System timing,” in Introduction to VLSI Systems, C. Mead and L. Conway, Eds., Addison-Wesley, Reading, Mass, USA, 1980, chapter 7. View at: Google Scholar
  10. J. Sparsø and S. Furber, Priciples of Asynchronous Circuit Design—A System Perspective, Kluwer Academic Publishers, Dordrecht, The Netherlands, 2001.
  11. D. Bertozzi, L. Benini, and G. De Micheli, “Error control schemes for on-chip communication links: the energy-reliability tradeoff,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 6, pp. 818–831, 2005. View at: Publisher Site | Google Scholar
  12. S. R. Sridhara and N. R. Shanbhag, “Coding for system-on-chip networks: a unified framework,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 6, pp. 655–667, 2005. View at: Publisher Site | Google Scholar
  13. L. Li, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, “Adaptive error protection for energy efficiency,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '03), pp. 2–7, San Jose, Calif, USA, November 2003. View at: Google Scholar
  14. H. Zimmer and A. Jantsch, “A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip,” in Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '03), pp. 188–193, Newport Beach, Calif, USA, October 2003. View at: Google Scholar
  15. R. E. Ziemer and R. L. Peterson, Introduction to Digital Communication, Prentice-Hall, Upper Saddle River, NJ, USA, 2nd edition, 2001.
  16. B. W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, Addison-Wesley, Reading, Mass, USA, 1989.
  17. C. Grecu, A. Ivanov, R. Saleh, and P. P. Pande, “NoC interconnect yield improvement using crosspoint redundancy,” in Proceedings of the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '06), pp. 457–465, Arlington, Va, USA, October 2006. View at: Publisher Site | Google Scholar
  18. I. E. Sutherland, “Micropipelines,” Communications of the ACM, vol. 32, no. 6, pp. 720–738, 1989, The 1988 Turing Award Lecture. View at: Publisher Site | Google Scholar
  19. A. Davis and S. M. Nowick, “Asynchronous circuit design: motivation, background and methods,” in Asynchronous Digital Circuit Design, G. Birtwistle and A. Davis, Eds., pp. 1–49, Springer, New York, NY, USA, 1995. View at: Google Scholar
  20. W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, Cambridge, UK, 1998.
  21. S. Murali, T. Theocharides, N. Vijaykrishnan, M. J. Irwin, L. Benini, and G. De Micheli, “Analysis of error recovery schemes for networks on chips,” IEEE Design & Test of Computers, vol. 22, no. 5, pp. 434–442, 2005. View at: Publisher Site | Google Scholar
  22. Handshake Solutions, http://www.handshakesolutions.com/.
  23. R. Hegde and N. R. Shanbhag, “Toward achieving energy efficiency in presence of deep submicron noise,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 4, pp. 379–391, 2000. View at: Publisher Site | Google Scholar
  24. W. J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks,” in Proceedings of the 38th Design Automation Conference, pp. 684–689, Las Vegas, Nev, USA, June 2001. View at: Google Scholar

Copyright © 2007 Teijo Lehtonen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Related articles

No related content is available yet for this article.
 PDF Download Citation Citation
 Order printed copiesOrder

Related articles

No related content is available yet for this article.

Article of the Year Award: Outstanding research contributions of 2021, as selected by our Chief Editors. Read the winning articles.