Table of Contents
VLSI Design
Volume 2007, Article ID 95402, 12 pages
Research Article

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

1VLSI Design Group, NVIDIA Corporation, Santa Clara 95050, CA, USA
2Electrical Enginering and Computer Science Department (EECS), Northwestern University, Evanston, 60208-3118, IL, USA
3Circuit Research Laboratories, Intel Corporation, Hillsboro 97124, OR, USA

Received 6 November 2006; Revised 27 February 2007; Accepted 16 March 2007

Academic Editor: Davide Bertozzi

Copyright © 2007 Maged Ghoneima et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [6 citations]

The following is the list of published articles that have cited the current article.

  • Daniele Ludovici, Alessandro Strano, Georgi N Gaydadjiev, Luca Benini, and Davide Bertozzi, “Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs,” 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp. 679–684, . View at Publisher · View at Google Scholar
  • Igor Loi, Federico Angiolini, and Luca Benini, “Developing mesochronous synchronizers to enable 3D NoCs,” Proceedings -Design, Automation and Test in Europe, DATE, pp. 1414–1419, 2008. View at Publisher · View at Google Scholar
  • Daniele Ludovici, Alessandro Strano, Davide Bertozzi, Luca Benini, and Georgi N. Gaydadjiev, “Comparing tightly and loosely coupled mesochronous synchronizers in a noc switch architecture,” Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009, pp. 244–249, 2009. View at Publisher · View at Google Scholar
  • Daniele Ludovici, Alessandro Strano, and Davide Bertozzi, “Architecture design principles for the integration of synchronization interfaces into network-on-chip switches,” 2nd International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO42, pp. 31–36, 2009. View at Publisher · View at Google Scholar
  • Faizal A. Samman, François Philipp, and Manfred Glesner, “Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems,” Proceedings of the 2011 1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments, CHANGE 2011, 2011. View at Publisher · View at Google Scholar
  • Dmitry Verbitsky, Rostislav Dobkin, Ran Ginosar, and Salomon Beer, “StarSync: An extendable standard-cell mesochronous synchronizer,” Integration, the VLSI Journal, vol. 47, no. 2, pp. 250–260, 2014. View at Publisher · View at Google Scholar