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VLSI Design
Volume 2007 (2007), Article ID 95402, 12 pages
Research Article

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

1VLSI Design Group, NVIDIA Corporation, Santa Clara 95050, CA, USA
2Electrical Enginering and Computer Science Department (EECS), Northwestern University, Evanston, 60208-3118, IL, USA
3Circuit Research Laboratories, Intel Corporation, Hillsboro 97124, OR, USA

Received 6 November 2006; Revised 27 February 2007; Accepted 16 March 2007

Academic Editor: Davide Bertozzi

Copyright © 2007 Maged Ghoneima et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Maged Ghoneima, Yehea Ismail, Muhammad Khellah, and Vivek De, “Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme,” VLSI Design, vol. 2007, Article ID 95402, 12 pages, 2007. doi:10.1155/2007/95402