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VLSI Design
Volume 2008 (2008), Article ID 109490, 14 pages
http://dx.doi.org/10.1155/2008/109490
Research Article

An Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product Codes

Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA

Received 1 June 2008; Accepted 14 October 2008

Academic Editor: Adam Postula

Copyright © 2008 Bo Fu and Paul Ampadu. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [7 citations]

The following is the list of published articles that have cited the current article.

  • Bo Fu, and P. Ampadu, “On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 9, pp. 2042–2054, 2009. View at Publisher · View at Google Scholar
  • B. Fu, and P. Ampadu, “Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects,” Iet Computers And Digital Techniques, vol. 4, no. 3, pp. 251–261, 2010. View at Publisher · View at Google Scholar
  • Melouki, Srivastava, and Al-Hashimi, “Fault-tolerance techniques for hybrid CMOS/nanoarchitecture,” IET Computers and Digital Techniques, vol. 4, no. 3, pp. 240–250, 2010. View at Publisher · View at Google Scholar
  • Qiaoyan Yu, and Paul Ampadu, “A Flexible Parallel Simulator for Networks-on-Chip With Error Control,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 1, pp. 103–116, 2010. View at Publisher · View at Google Scholar
  • Samee Ullah Khan, Masud Al Aziz, Thanasis Loukopoulos, Pascal Bouvry, Hongxiang Li, and Juan Li, “An overview of achieving energy efficiency in on-chip networks,” International Journal of Communication Networks and Distributed Systems, vol. 5, no. 4, pp. 444–458, 2010. View at Publisher · View at Google Scholar
  • M. Maheswari, and G. Seetharaman, “Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links,” Microprocessors and Microsystems, 2013. View at Publisher · View at Google Scholar
  • M. Maheswari, and G. Seetharaman, “Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link,” Journal of Electronic Testing, 2014. View at Publisher · View at Google Scholar