An Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product Codes

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="109490.fig.010a" src="https://static.hindawi.com/articles/vlsi/volume-2008/109490/figures/109490.fig.010a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Column decoder</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="109490.fig.010b" src="https://static.hindawi.com/articles/vlsi/volume-2008/109490/figures/109490.fig.010b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Combinational ones counter</td></tr></table></td></tr></table>

<table>Implementation of the column decoder
 in the proposed iterative decoding method.</table>

VLSI Design

fig10

Figure 10

Figure 10: An Energy-Efficient Multiwire Error Control Scheme for Reliable On-Chip Interconnects Using Hamming Product Codes 