A Programmable Hardware Cellular Automaton: Example of Data Flow Transformation

Table 2

Encryption cores resource and performance.

Core	Std Helion	PHCA	ISM
Application	AES	ISEA 32×32 sites	ISEA 32×32 sites
Technology	Spartan 3–5	Spartan xc3s5000	Spartan xc3s5000
Logic resource	251 slices 3 block rams	32589 slices	14148 slices
Max clock frequency	151 MHz	161 MHz	132 MHz
Max data rate	402 Mbps	16 Mbps	2110 Mbps
Programmable	No (dedicated to AES)	Yes (with 1D or 2D AC rules)	No (dedicated to ISEA)