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VLSI Design
Volume 2008 (2008), Article ID 259281, 7 pages
Research Article

A Robust Low-Voltage On-Chip LDO Voltage Regulator in 180 nm

Electronics and Communication Engineering Department, Chip Design Cener, National Institute of Technology, Warangal 506004, India

Received 10 August 2008; Accepted 23 October 2008

Academic Editor: Yong-Bin Kim

Copyright © 2008 Sreehari Rao Patri and K. S. R. Krishna Prasad. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper proposes a capacitor-less LDO with improved steady-state response and reduced transient overshoots and undershoots. The novelty in this approach is that the regulation is improved to a greater extent by the improved error amplifier in addition to improved transient response against five vital process corners. Also entire quiescent current required is kept below 100  𝜇 A . This LDO voltage regulator provides a constant 1.2 V output voltage against all load currents from zero to 50 mA with a maximum voltage drop of 200 mV. It is designed and tested using Spectre, targeted to be fabricated on UMC 180 nm.