Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver

<table>BER degradation comparing the floating-point version of the
MIMO decoder (solid lines with marker “o”) and its fixed-point counterpart
implementation Q2 (dashed lines with marker “x”).</table>

VLSI Design

fig5

Figure 5

Figure 5: Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver 