A Programmable Max-Log-MAP Turbo Decoder Implementation

<table>Proposed memory
structure with buffered write operations. Word length of data and address pair
is denoted with WL. Indices in brackets index the bus connected to the <svg height="14.3625" id="M68" style="vertical-align:-3.2316pt" version="1.1" viewbox="0 0 16.950001 14.3625" width="16.950001" xmlns="http://www.w3.org/2000/svg">
<g transform="matrix(1.25,0,0,-1.25,0,14.3625)">
<g transform="translate(72,-60.51)">
<text transform="matrix(1,0,0,-1,-71.95,63.79)">
<tspan style="font-size: 12.50px; " x="0" y="0">𝐿</tspan>
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<text transform="matrix(1,0,0,-1,-63.1,60.66)">
<tspan style="font-size: 8.75px; " x="0" y="0">𝑏</tspan>
</text>
</g>
</g>
</svg> length buffer.</table>

VLSI Design

A Programmable Max-Log-MAP Turbo Decoder Implementation

Figure 5