A Programmable Max-Log-MAP Turbo Decoder Implementation

Table 2

Complexity and throughput of the turbo decoder TTA processor.

Clock frequency	Area	Throughput 1 iteration	Throughput 6 iterations
100 MHz	27.9 kgates	49 Mbps	8.2 Mbps
200 MHz	31.9 kgates	98 Mbps	16.4 Mbps
250 MHz	35.7 kgates	123 Mbps	20.5 Mbps
277 MHz	43.2 kgates	136 Mbps	22.7 Mbps