A Programmable Max-Log-MAP Turbo Decoder Implementation

Table 3

Comparison of turbo decoder implementations.

Category	Reference	Architecture/technology	Clock frequency	Area	Throughput 1 iteration	Algorithm	Cycles/stage (𝐶stage)
Pure HW design	[10]	180 nm technology	145 MHz	410 kgates	144 Mbps	log-MAP	0.50
	[11]	Virtex 5 FPGA	310 MHz	—	139 Mbps	MAX SCALE	1.12
	[35]	130 nm technology	246 MHz	44.1 kgates	112 Mbps	max-log-MAP	1.10
	[12]	Virtex 2 FPGA	56 MHz	—	79.2 Mbps	MAP	0.35
	[36]	180 nm technology	100 MHz	115 kgates	27.1 Mbps	max-log-MAP	1.84
	[37]	180 nm technology	111 MHz	85.0 kgates	25 Mbps	log-MAP	2.21
	[20]	180 nm technology	133 MHz	24.0 kgates	22.8 Mbps	log-MAP	2.92
Monolithic accelerator	[13, 38]	Turbo coprocessor of C64x	300 MHz	86.6 kgates	90.4 Mbps	log-MAP	1.66
	[14]	SISO dec. with SIMD	135 MHz	34.4 kgates	32.9 Mbps	[max]-log-MAP	2.05
Programmable processor	Proposed	TTA proc. (130 nm)	277 MHz	43.2 kgates	136 Mbps	max-log-MAP	1.02
	[8]	SIMD ASIP (65 nm)	400 MHz	64.1 kgates	100 Mbps	log-MAP	2.00
	[4]	TTA proc. (130 nm)	210 MHz	20.8 kgates	14.1 Mbps	max-log-MAP	7.46
	[9]	SIMD DSP	400 MHz	—	10.4 Mbps	max-log-MAP	19.2
	[5]	TigerSHARC DSP	250 MHz	—	9.6 Mbps	max-log-MAP	13.0
	[39, 40]	VLIW ASIP (FPGA)	80 MHz	—	5.0 Mbps	max-log-MAP	8.00
	[6]	SP-5 SuperSIMD DSP	250 MHz	—	4.7 Mbps	max-log-MAP	26.9
	[7]	C62x VLIW DSP	300 MHz	—	4.4 Mbps	max-log-MAP	34.5
	[41]	ST120 VLIW DSP	200 MHz	—	2.7 Mbps	max-log-MAP	37.0
	[42]	C55x DSP	300 MHz	—	2.0 Mbps	max-log-MAP	74.8
	[43]	PC with Pentium III	933 MHz	—	366 kbps	max-log-MAP	1275
	[44]	XiRisc reconf. proc. (FPGA)	100 MHz	—	270 kbps	log-MAP	185
	[41]	DSP56603 DSP	80 MHz	—	243 kbps	max-log-MAP	165