Table of Contents
VLSI Design
Volume 2008, Article ID 479173, 6 pages
Research Article

Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

1Microelectronics and Computer Department, Faculty of Electrical Engineering, University of Technology Malaysia, 81310 Skudai, Johor, Malaysia
2Device Modeling Department, Silterra Malaysia Sdn. Bhd., 09000 Kulim, Kedah, Malaysia

Received 13 June 2007; Accepted 17 December 2007

Academic Editor: Jose Silva-Martinez

Copyright © 2007 Ler Chun Lee et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA) has been designed using Silterra's industry standard 0.18  RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA). A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of  dB, S22 of  dB, and input 1 dB compression point of  dBm at 3 GHz

1. Introduction

Recently, direct-conversion and low-intermediate frequency (low-IF) receivers have become highly popular choices in RFIC since they avoid the need for expensive external passive components such as surface-acoustic wave (SAW) filters for image rejection. Unfortunately, serious problems do exist for direct-conversion and low-IF receivers. The direct-conversion receiver is very sensitive to DC offset and low-frequency interference signals. Since IF of the direct-conversion receiver is zero, there is a little doubt that flicker noise will produce a maximum negative effect in direct-conversion receivers. A low-IF receiver has many of the attributes of a direct-conversion receiver but has lower sensitivity to DC offsets and flicker noise. However, the image rejection problem reappears [1].

The superheterodyne receiver is the most widely used receiver front-end architecture and exhibits good RF performance. Proper image signal filtering is required. This can be done by using external SAW filters. The drawbacks of using SAW filters are increased cost and device size [2]. To overcome these problems, recent research has focused on IRLNA that uses a notch filter to reject the image signals [36].

Unlike on-chip spiral inductors, active inductors have smaller die area, larger inductance, higher-quality factor (), tunable inductance, and . The of the spiral inductor is usually low, this being due to the wiring and substrate losses. Unfortunately, active inductors have poor noise performance, poor linearity, and higher-power dissipation, and are more sensitive to process, voltage supply, and temperature (PVT) variation compared to spiral inductors.

The paper is organized as follows: Section 2 introduces the concept and design of active inductors. Section 3 discusses several popular types of IRLNA that have been reported in the literature. The proposed IRLNA designed using an active inductor is presented in Section 4, with measurement results. Section 5 concludes the paper.

2. Active Inductor Circuit Design

Active inductor is an attractive alternative to low- on-chip spiral inductors. For monolithic RFIC applications, the design of the active inductor using gyrator is best described in Figure 1(a). , , , and are parasitic conductance and capacitance, respectively. and represent transconductors and are connected back-to-back to form a gyrator. The input admittance of the gyrator circuit, , is shown as follows:

Figure 1: (a) Active inductor for RFIC applications; (b) simplified model for active inductor.

The third item in (1) behaves as an inductor with resistive loss. Based on (1), the active inductor can be modeled as a resonator as shown in Figure 1(b), where

The active inductor proposed in [7] was used in this design. The simplified circuit design of the active inductor is shown in Figure 2. According to [7], if , then

Figure 2: Simplified circuit diagram of the active inductor used in this design.

where and are the parasitic conductance and capacitance at node 3, respectively. The input admittance, in Figure 2, can be calculated from (1) and (3) as follows:

From (4), the inductance can be tuned by varying , while of the active inductor can be tuned by varying . Hence, two varactors are added at node 2 and node 3 for inductance and tuning, respectively.

3. Overview of Existing IRLNA Design

3.1. Second-and Third-Order Active Notch Filters

The first fully integrated IRLNA using a second-order active filter was introduced in [8] using 0.5 m bipolar technology with 25 GHz transit frequency. The second-order active notch filter is based on a series LC resonator that resonates at the image frequency. Figure 3(a) shows the cascade LNA with the second-order active filter. The input impedance of the second-order active notch filter is given by [8] where , , and are the emitter-base capacitance, transconductance, and base resistance of . is the resistive loss of the inductor. At image frequency, the input impedance of the active notch filter becomes minimum. That will decrease the gain of the LNA. However, the notch filter might have negative impact on the LNA because the input impedance of the second-order active notch filter might be lower than the case without the filter. The power gain and noise figure of the IRLNA will degrade due to the signal loss.

Figure 3: IRLNA with (a) second-order active notch filter and (b) third-order active notch filter.

To overcome the limitation of the IRLNA proposed in [8], a CMOS third-order active notch filter has been proposed in [5], as shown in Figure 3(b). Assuming that all the parasitic components are cancelled, the input impedance of the active notch filter now can be expressed as follows [5]: where and .

From (6), the active notch filter proposed in [5] can have high impedance at the wanted signal frequency and low impedance at the image signal frequency.

3.2. Third-Order Passive Notch Filter

Third-order passive notch filter technique was proposed in [3] for CMOS IRLNA, as shown in Figure 4. The input impedance of the passive notch filter as given by [3] is the following:

Figure 4: CMOS IRLNA with third-order passive notch filter.

Similar to the notch filter proposed in [5], the passive notch filter shown in Figure 4 has low and high input impedance at image signal frequency and wanted signal frequency, respectively. Since CMOS spiral inductors usually have very low , a cross-connected differential transistor pair has been used as a negative impedance circuit to increase of the notch filter. The notch frequency tuning of the IRLNA can be done by using varactor .

4. Proposed IRLNA Using Active Inductor

Since spiral inductors consume large die area compared to active devices, the use of active inductor to replace spiral inductor becomes an attractive choice for notch filters. Circuit diagram of the proposed IRLNA using active inductor is shown in Figure 5. The spiral inductor in the notch filter in Figure 4 has been replaced by an active inductor. Since the notch frequency of the image-rejection notch filter can be tuned by the active inductor, the varactor in Figure 4 can be eliminated. If the of the active inductor is high enough, the input impedance of the notch filter shown in Figure 5 is approximated by (7).

Figure 5: Complete schematic for the proposed IRLNA.

The wanted signal frequency and image signal frequency are located at

The active inductor shown in Figure 2 is used to implement our proposed IRLNA. The active die area for the active inductor including DC biasing circuits is m2, which is much smaller than a spiral inductor that typically requires m2. As mentioned in Section 2, two NMOSs in N-well varactors were added at node 2 and node 3 for inductance and tuning, respectively. The proposed IRLNA adopts popular source-degenerated LNA architecture for low-noise, which is shown in Figure 5. An extra capacitor together with and is used to obtain power-constrained simultaneous noise and input matching [5].

As mentioned before, together with the active inductor forms a third-order notch filter for image rejection. All the devices shown in Figure 5 are implemented on-chip.

The proposed IRLNA was fabricated using Silterra’s 0.18 m industry standard RF CMOS process. For comparison, an LNA identical to the proposed IRLNA but without notch filter was included in the fabrication. The die micrograph of the LNA and IRLNA is shown in Figure 6. All the DC, S-parameters, and noise figure measurements were performed on wafer using Cascade Microtech’s RF probe station with GSG Infinity probes. Due to the DC biasing startup circuit problem, the actual DC biasing active inductor is different from the predicted value. Current sources located at node 1 and node 2 of the active inductor operate in linear region and this lowers of the active inductor. Measured of the active inductor returns a value of around 5 to 8, and this is lower than the expected value. The low- active inductor has a negative impact on the gain and noise performance of the IRLNA.

Figure 6: Die micrograph for (a) proposed IRLNA and (b) LNA.

S-parameters of the IRLNA and LNA are shown in Figures 7 and 8. As can be observed from Figure 7, the notch filter designed using active inductor can provide additional 8.25 dB image rejection at 1.42 GHz. An active inductor with higher would further improve the image-rejection of the notch filter. A comparison between the performance of the proposed IRLNA and the LNA is shown in Table 1. S21 of the proposed IRLNA is 2.8 dB lower than the LNA, which is mainly due to the low- active inductor.

Table 1: Comparison between proposed IRLNA and LNA.
Figure 7: S21 of LNA and proposed IRLNA.
Figure 8: S11 and S22 of LNA and proposed IRLNA.

In Table 1, the noise figures (NFs) of the LNA and IRLNA are much higher than simulation results. The excess noise is contributed from the losses of Cascade Microtech high-frequency cable and GSG Infinity probe that precede the LNA and IRLNA. The calibration of the noise figure analyzer is unable to remove these losses. Further experiments showed that the Cascade Microtech high-frequency cable has additional loss around 1.3 dB compared to Agilent coaxial cable 11500F. Hence, it is reasonable to estimate that the loss preceding the LNA, including the input GSG Infinity probe, is at least 2 dB. In addition, system port mismatch due to the on-wafer NF measurement will further increase the uncertainties of the NF measurement [9]. Besides that, there is additional noise probably contributed by the DC power supply itself. Adding a large capacitor between VDD and ground can reduce that problem.

However, comparing noise factor difference () between IRLNA and LNA, the measured (after de-embedding) is 56% higher than simulation results. The discrepancy of between measurement and simulation may be due to several factors mentioned below.(a)Low- active inductor (due to the DC biasing circuit) results in lower gain of the LNA at the operating frequency. This can be observed from S21 of the LNA and IRLNA shown in Table 1. IRLNA’s NF increases due to the lower gain.(b)Actual losses preceding the LNA in the NF measurement system are more than 2 dB if all the losses (e.g., adapter loss and input port mismatch) are taken into consideration. Discrepancy of in measurement and simulation will be smaller if all the losses preceding LNA are considered.(c)Noise contributed from the active inductor is underestimated. Short-channel NMOS devices contribute more thermal noise than the value predicted by long-channel theory [10]. Long-channel thermal noise equation was used in the simulation.

Thanks to the active inductor, the actual die area occupied by the proposed IRLNA is approximately the same as the LNA.

Besides noise performance, sensitivity of the active inductor to PVT variations is also a very important design challenge that needs to be considered. of the MOSFET is the most sensitive parameter to PVT variations in the active inductor. A wider notch frequency tuning range can overcome PVT variations. Some applications like HIPERLAN require a tuning range of 150 MHz, whereas 802.11a requires tuning range of 675 MHz to cover the desired frequency band [1, 3]. The tuning range of the active inductor notch filter in this paper is limited by the varactor tuning range. A higher tuning range could be obtained by tuning MOSFET’s , rather than using varactors. The tuning range () of active inductors can reach more than [11], which is sufficient to cover all the desired frequency bands and PVT variations.

5. Conclusion

Although the active inductor is noisy and has limited dynamic range compared to spiral inductors, in this paper we show that it is usable for IRLNA design. With proper design, the noise contribution from the active inductor can be reduced to its minimum level. Further improvements are still in progress, which aim to reduce the active inductor’s noise contribution, power dissipation, and increase its frequency tuning range to compensate PVT variations.


The authors would like to thank Silterra Malaysia Sdn. Bhd. for the chip fabrication and Associate Professor Dr. Othman Sidek of Collaborative MicroElectronic Design Excellence Centre (CEDEC) for the CEDEC's measurement system. The authors would also like to thank Dr. Tun Zainal and Mohd. Shukri for their valuable help and discussion.


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