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VLSI Design
Volume 2008, Article ID 512946, 8 pages
http://dx.doi.org/10.1155/2008/512946
Research Article

A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

Department of Electrical Engineering, National Sun Yat-Sen University, 70 Lian-Hai Road, Kaohsiung 80424, Taiwan

Received 28 January 2008; Revised 3 July 2008; Accepted 31 July 2008

Academic Editor: Wieslaw Kuzmicz

Copyright © 2008 Tzung-Je Lee and Chua-Chin Wang. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Charlamov, and Navickas, “Phase locked loop integrated system,” Solid State Phenomena, vol. 164, pp. 221–226, 2010. View at Publisher · View at Google Scholar
  • Jeffrey S. Pulskamp, Luz M. Sanchez, Daniel M. Potrepka, Robert M. Proie, Tony G. Ivanov, Ryan Q. Rudy, William D. Nothwang, Sarah S. Bedair, Christopher D. Meyer, and Ronald G. Polcawich, “PZT-Based Piezoelectric MEMS Technology,” Journal of The American Ceramic Society, vol. 95, no. 6, pp. 1777–1792, 2012. View at Publisher · View at Google Scholar
  • Nam Pham, Faraydon Pakbaz, Zhenrong Jin, and Lloyd Walls, “Power supply filter for PLL circuit in digital systems,” Proceedings - Electronic Components and Technology Conference, pp. 535–540, 2014. View at Publisher · View at Google Scholar