A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

<table>The
measurement jitter histogram of the proposed PLL with the 250 mVrms supply
noise. (a) The supply noise is provided to the dual regulators. (b) The supply
noise is coupled directly to the CP and the VCO.</table>

VLSI Design

fig10

Figure 10

Figure 10: A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators 