A Phase-Locked Loop with 30% Jitter Reduction Using Separate Regulators

Table 1

Performance comparison of the proposed PLL and prior works.

	Ours	[5]	[12]
CMOS process (S)	0.35 𝜇m	0.5 𝜇m	0.35 𝜇m
Supply voltage (Vsp)	3.3 V	3.3 V	3.3 V
Power consumption (P @ 𝑓)	78 mW @ 80 MHz	9.24 mW @ 550MHz^♭	200 mW @ 125MHz^♭
FOM1^#	0.731	0.006	1.199
P2P jitter	81.8 ps @ 250 mVrms	144 ps @ 500 mV/1 MHz	222 ps @ N/A
	supply noise	square wave supply noise
Core area (A)	0.516 mm^2	1.91 mm^2	2.89 mm^2
FOM2^#	4.21	7.64	23.59
Topologies	Dual regulators	Self-biased & differential structure	Time-constant calibration

#: FOM1=P/(𝑓S²Vsp²), FOM2 = A/(S²), where S is the feature size of the process.♭: Assume that the power consumption is measured at the maximum operating frequency.