An FFT Core for DVB-T/DVB-H Receivers

Table 7

Chip summary of our FFT processor.

Items	Specification
FFT size	2K/4K/8K
Clock frequency	64/7 MHz
Data bitwidth (dbw)	16 bits
Twiddle factor bitwidth (tbw)	11 bits
Signal-to-quantization-noise ratio (SQNR) for 𝑁max=8K	40.6 dB
Process technology	0.35 μm XFAB 4-ML
Supply voltage	3.3 V
Execution time (clock cycles) for 𝑁=2K	1040 clock cycles
Execution time (clock cycles) for 𝑁=4K	2064 clock cycles
Execution time (clock cycles) for 𝑁max=8K	4115 clock cycles
Core power consumption for 𝑁max=8K	114.65 mW
Core size	18.7 mm^2