A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences

Table 4

Simulation results for the ISCAS’85 circuits.

Crc	No. of Inp	No. of Vec	Test length			Diff %
			[11]	[16]	Proposed
c499	41	51	1 642 559 798 913	1 633 341 388 679	1 841 099 032 209	≈2 97
C432	36	45	52 907 549 189	*	60 666 416 672	≈14 66%
c880	60	53	1 103 035 270 379 361 210	1 103 035 270 379 361 210	1 048 857 218 160 706 800	≈−4 91%
c1355	41	86	1 881 067 490 587	1 875 129 180 656	2 047 414 822 299	≈5 26
c1908	33	116	7 517 790 261	7 517 790 261	6 442 450 947	≈−14 99
c3540	50	145	981 672 975 771 693	953 512 009 096 806	1 083 104 061 625 293	≈9 89
c6288	32	28	2 146 503 245	2 146 503 245	3 871 357 360	≈54 46
Calculation time			>10 min	>20 s	<0.7 s

^*Not available in [16].