Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2008, Article ID 847932, 5 pages
http://dx.doi.org/10.1155/2008/847932
Research Article

Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers

1Electronics and Communication Engineering Department, Thapar University, Patiala, Punjab 147004, India
2Central Electronics Engineering Research Institute (CEERI), Council of Scientific and Industrial Research (CSIR), Pilani, Rajasthan 333031, India

Received 23 April 2007; Accepted 18 December 2007

Academic Editor: Jose Silva-Martinez

Copyright © 2008 Alpana Agarwal and Chandra Shekhar. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A new methodology based on the concept of figure of merit under area constraints is described for designing optimum performance differential amplifiers. First a figure of merit is introduced that includes the three performance parameters, namely, input-referred noise, differential dc gain, and unity-gain bandwidth. Expressions for these parameters have been derived analytically and finally arrived at an expression for the figure of merit. Next it is shown how these performance parameters vary with the relative allocation of the total available area between the input and load transistors. The figure of merit peaks at a certain value of relative area allocation in the range of 60% to 80% of the available area to the input transistors. The peak value of figure of merit is a function of area. However, it is independent of biasing current (and, therefore, power consumption) subject to the minimum current (and, therefore, a minimum power) required to keep all the transistors biased in the saturation region. The peak figure of merit and minimum power required to achieve the peak figure of merit are also plotted as a function of area. These analyses help in synthesizing optimal differential amplifier circuit designs under area constraints.

1. Introduction

The first stage of an operational amplifier and several types of comparators is typically a differential amplifier that needs to provide sufficient gain and bandwidth while introducing as little noise as possible. Moreover, if this is desired with a constraint on area, the problem becomes more difficult. The classical noise optimization techniques for low noise amplifier (LNA) design presume a device given with fixed characteristics, and thus offer no explicit guidance on how to best exercise the IC designer’s freedom in tailoring device geometries under the constraints of area [1].

2. Concept of Figure of Merit

To compare different solutions for an analog circuit design, first a figure of merit must be agreed upon. One of the key issues is the design of a circuit with maximal figure of merit under constraints of area. Here, a figure of merit has been proposed that takes into account the three key performance parameters, that is, the differential dc gain, unity-gain bandwidth, and input-referred noise. The proposed figure of merit in this paper is given by where UGB is the unity-gain bandwidth, Ad is the differential dc gain, and IRN is the peak input-referred noise spectral density; the differential amplifier illustrated in Figure 1.

47932.fig.001
Figure 1: Differential amplifier.

3. Performance Parameters

3.1. Noise Model for Most

Each semiconductor device in the circuit introduces noise. Various types of noises that could be possible in a device are shot, thermal, flicker (), avalanche, burst, and so forth.

At low frequencies, flicker () noise dominates all other noises. Therefore, here only flicker noise has been considered to introduce the concept developed.

There exist numerous models for flicker noise in the MOS transistor [210]. According to the most popular model [10], the flicker noise due to a MOS transistor can be lumped as a voltage source at the gate and is given by in the noise bandwidth of at frequency . and are the effective width and length of the gate of the MOS transistor, is the flicker noise coefficient for the MOS transistor, and is the gate capacitance per unit area.

However, the overall circuit noise depends on the circuit configuration.

3.2. Input-Referred Noise

For the differential amplifier shown in Figure 1, there are four voltage noise sources connected at the gate of each transistor. If all these sources are lumped together at the gate of transistor M1, the mean-square value of the equivalent noise voltage source at input (gate of M1) for the total circuit noise is given by where , , , are the noise sources at the gates of transistors M1, M2, M3, and M4. and are the transconductance of the input (M1 and M2) and load (M3 and M4) transistors, respectively, and are given by where , , , and are the widths and lengths of input and load transistors, respectively, and are the process transconductance parameters for -channel and -channel MOS transistors, and is the tail current of the differential amplifier.

Using (2), (3), and (4), the power spectral density of noise at the gate of M1 is written as Therefore, root-mean-square value of spectral power density better known as input-referred noise at frequency is written as

3.3. Unity-Gain Bandwidth

Unity-gain bandwidth of the circuit, UGB, is given by as is the total load capacitance at the output node.

3.4. Differential dc Gain

The differential dc gain, Ad, of the differential amplifier is given by where and are the drain to source conductance of input and load transistors, respectively. The drain to source conductance is approximated as where (known as channel-length modulation parameter) is a process parameter [11], and its value has been taken as 0.1 μm/V for NMOS and 0.05 μm/V for PMOS transistors.

3.5. Figure of Merit

Substituting the values of UGB, Ad, and IRN from (6), (7), and (8) in (1), we get the following:

4. Maximization of Figure of Merit under Area Constraints

If is the total area available for the devices in the differential amplifier, then let us assign % of , that is, to the input transistors and to load transistors. Then, writing the expressions for UGB, Ad, and peak IRN (at ) in terms of , area (), bias current (), and technology parameters, we get Hence, from (1) and (11) figure of merit (FoM) in terms of , area (), bias current (), and technology parameters is written as From (12), the following conclusions can be drawn.

(i)Figure of merit, FoM, is dependent on technology parameters, , , , , .(ii)It is inversely proportional to the output load .(iii)To maximize FoM, length of input transistor should be kept minimum for a given area , as it maximizes all the three product terms wherever it appears.(iv)Figure of merit is independent of the width of load transistor, , hence it should be kept as minimum.(v)Length of load transistor should be as large as possible under the constraints of area since it maximizes the last two product terms and hence maximizes figure of merit FoM.

5. Analytical Results

Figure 2 shows the variation of differential dc gain as a function of relative area allocated to input transistors at different values of total area. It is clear that as the total area increases, the differential dc gain increases. But it does not keep on increasing with the increase in input transistors area. The peak value of dc gain is obtained for in the range of 0.6 to 0.8. Figure 3 shows that the unity-gain bandwidth is a monotonically increasing function of .

47932.fig.002
Figure 2: The differential dc gain as a function of input transistor area.
47932.fig.003
Figure 3: Unity-gain bandwidth (in MHz) as a function of input transistor area.

The variation of peak value of input-referred noise as a function of is shown in Figure 4. For larger values of , the noise is reducing because with increasing , the gate area of input transistors is increasing and their noise contribution is decreasing. But it is interesting to note that it starts increasing beyond a point for all the values of . It implies that beyond this point, the contribution of noise from load transistors over and above the contribution of input transistors increases.

47932.fig.004
Figure 4: Input-referred noise (in μV/rt (Hz)) as a function of input transistor area.

Next the figure of merit is plotted as a function of percent area allocated to input transistors. Figure of merit is a peaking function of in the range 60% to 80% as shown in Figure 5. It is clear that figure of merit increases with total area .

47932.fig.005
Figure 5: The figure of merit, FoM, (in *1012 Hz3/2/V) as a function of input transistor area.

It also indicates that for a fixed value of total area, about how much percent of total area should be assigned to input transistors to obtain a maximum value of figure of merit. Peak value of figure of merit as a function of total area is plotted in Figure 6.

47932.fig.006
Figure 6: Peak value of figure of merit, FoM, as a function of area.

The value of figure of merit is independent of bias current . However, a minimum value of power is essential to keep all the transistors in saturation. Figure 7 shows the minimum bias current required for keeping all the transistors in the circuit in saturation region (and in strong inversion) as a function of total area. It implies that for a given area, a minimum power has to be provided. To increase the figure of merit, area increase alone is not enough; more power is also required to keep the transistors in saturation.

47932.fig.007
Figure 7: Minimum power desired as a function of total area.

6. Simulation Results

Simulations using Tanner Tools Pro also validated the analytical results. To perform this task, a value of total area was chosen. The total area was divided between input and load transistors in a predefined ratio. Then, for this distribution of areas, all combinations of aspect ratio of input and load transistors were simulated to obtain the differential dc gain, unity-gain bandwidth, and peak value of input-referred noise. The figure of merit was computed from these parameters. The peak figure of merit as a function of input transistor area in percent (ratio of area allocated to input transistors to the total available area ) for various values of total area is plotted as shown in Figure 8. This plot matches well with the analytical results shown in the previous section.

47932.fig.008
Figure 8: Simulated plot of figure of merit, FoM, (in *1012 Hz3/2/V) as a function of input transistor area.

In order to demonstrate the utility of figure of merit as a tool to optimize the design, we define three new parameters as follows:Ad%is the differential dc gain at peak figure of merit as a percentage of maximum differential dc gain achievable for a given area;UGB%is unity-gain bandwidth at peak figure of merit as a percentage of maximum unity-gain bandwidth achievable for a given area;IRN%is input-referred noise at peak figure of merit as a percentage of minimum input-referred noise achievable for a given area.

Table 1 compares the analytical and simulated values of peak figure of merit, Ad%, UGB%, and IRN% for constant area. In most cases, value of Ad% is more than 95%, and the value of UGB% is more than 91%. IRN% is less than 101% in all cases.

tab1
Table 1: Comparison between analytical and simulated performance at peak figure of merit.

7. Conclusion

The concept of figure of merit is a suitable tool for synthesizing optimal design of differential amplifiers under area constraints and leads to the realization of differential dc gain, unity-gain bandwidth, and input-referred noise values that are also very close to their individually achievable maximum values under the same area constraints. The above analyses validate that the idea of FoM may be deployed in a CAD tool for automatically synthesizing the differential amplifiers and can be extended for many other building blocks for low frequency applications. The paper also highlights the dependence of peak figure of merit and the minimum power required to achieve it on the area available for the circuit.

Acknowledgments

The authors acknowledge the financial support provided by Ministry of Communication and Information Technology, New Delhi through SMDP-VLSI Program. Alpana Agarwal also thanks the Director of Thapar University, Patiala, India, for providing constant support and encouragement.

References

  1. D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 745–759, 1997. View at Publisher · View at Google Scholar
  2. K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,” IEEE Transactions on Electron Devices, vol. 37, no. 3, part 1, pp. 654–665, 1990. View at Publisher · View at Google Scholar
  3. J. Chang, A. A. Abidi, and C. R. Viswanathan, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures,” IEEE Transactions on Electron Devices, vol. 41, no. 11, pp. 1965–1971, 1994. View at Publisher · View at Google Scholar
  4. C. Jakobson, I. Bloom, and Y. Nemirovsky, “1/f noise in CMOS transistors for analog applications from subthreshold to saturation,” Solid-State Electronics, vol. 42, no. 10, pp. 1807–1817, 1998. View at Publisher · View at Google Scholar
  5. A. Arnaud and C. Galup-Montoro, “Consistent noise models for analysis and design of CMOS circuits,” IEEE Transactions on Circuits and Systems I, vol. 51, no. 10, pp. 1909–1915, 2004. View at Publisher · View at Google Scholar
  6. D. Xie, M. Cheng, and L. Forbes, “SPICE models for flicker noise in n-MOSFETs from subthreshold to strong inversion,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 11, pp. 1293–1303, 2000. View at Publisher · View at Google Scholar
  7. J. Zhou, M. Cheng, and L. Forbes, “SPICE models for flicker noise in p-MOSFETs in the saturation region,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 6, pp. 763–767, 2001. View at Publisher · View at Google Scholar
  8. A. Arnaud and C. Galup-Montoro, “A compact model for flicker noise in MOS transistors for analog circuit design,” IEEE Transactions on Electron Devices, vol. 50, no. 8, pp. 1815–1818, 2003. View at Publisher · View at Google Scholar
  9. E. P. Vandamme and L. K. J. Vandamme, “Critical discussion on unified 1/f noise models for MOSFETs,” IEEE Transactions on Electron Devices, vol. 47, no. 11, pp. 2146–2152, 2000. View at Publisher · View at Google Scholar
  10. P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, New York, NY, USA, 4th edition, 2001.
  11. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, New York, NY, USA, 3rd edition, 1992.