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VLSI Design
/
2009
/
Article
/
Tab 10
/
Research Article
Floorplan-Driven Multivoltage High-Level Synthesis
Table 10
Energy reduction (%) comparisons.
Benchmark
[
6
]
FloM
Wire
Datapath
Wire
Datapath
FDCT
35.63
52.70
FIR
37.79
36.80
DiffEq
29.05
39.60
Average
41.24
42.60