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VLSI Design
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Special Issues
VLSI Design
/
2009
/
Article
/
Tab 2
/
Research Article
Floorplan-Driven Multivoltage High-Level Synthesis
Table 2
Delay and energy characterization of FUs.
FU
5.0 V
3.3 V
2.4 V
D
E
D
E
D
E
ALU
25.7
57
45.5
25
76.8
13
Multiplier
54.0
2202
96.6
960
163.7
507
Mux
—
9
—
4
—
2