Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications

<table>Change in <svg height="15.4375" id="M167" style="vertical-align:-3.41936pt" version="1.1" viewbox="0 0 25.799999 15.4375" width="25.799999" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> =  0.2 V  [<a href="/journals/vlsi/2009/283702/#B14">14</a>].</table>

VLSI Design

fig10

Figure 10

Figure 10: Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications 

VLSI Design

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Figure 10