Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications

<table>Region of operation of digital
subthreshold logic [<a href="/journals/vlsi/2009/283702/#B9">9</a>].</table>

VLSI Design

Figure 2: Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications 