Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications

<table>Inverter delay versus gate length [<a href="/journals/vlsi/2009/283702/#B13">13</a>].</table>

VLSI Design

Figure 4: Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications 