Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications

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</svg> characteristics of DG NMOSFETs
with different gate lengths [<a href="/journals/vlsi/2009/283702/#B13">13</a>].</table>

VLSI Design

fig5

Figure 5

Figure 5: Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications 

VLSI Design

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Figure 5