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Review Article

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Table 2

Device-and circuit-level implications due to device sizing using RSCE [11].

ParameterAt the device levelAt the circuit-level

S (mV/dec)71 (16 mV less)
2.5X improvement
Device capacitanceLow
Process variationsReduce
Avg. delay13% improvement
Avg. power31% reduction
Op. frequency100 MHz
PDP (energy)40% reduction

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