Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Table 2

Device-and circuit-level implications due to device sizing using RSCE [11].

Parameter	At the device level	At the circuit-level
S (mV/dec)	71 (16 mV less)	—
𝐼ON/𝐼OFF	2.5X improvement	—
Device capacitance	Low	—
Process variations	—	Reduce
Avg. delay	—	13% improvement
Avg. power	—	31% reduction
Op. frequency	—	100 MHz
PDP (energy)	—	40% reduction