VLSI Design

VLSI Design / 2009 / Article / Tab 3

Review Article

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Table 3

Using optimum under lap [14].

S.NO.ParameterEffect compared with overlap DGMOS

(1)delay40% improvement
(2)Effective Reduced by 8
(3)energyLess by 6.2
(4)Frequency1.2 GHz
(5)PDP7.3 reduction

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