VLSI Design

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Review Article

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Table 4

Comparing bulk CMOS and DGSOI @ =200 mV) at iso- of 1 nA/um [16].

ParameterBulk CMOSDGSOI

for standard device (A/m)0.1011.29
for optimized device (A/m)0.1621.93
PDP of an inverter with standard device (J)5.5 10−160.35 10−16
PDP of a CMOS inverter with optimized device (J)2.8 10−160.30 10−16
(48% better than standard)(17% better than standard)
PDP of a Sub-Pseudo-NMOS inverter with optimized device (J)2.2 10−160.25 10−16
Power-throughput tradeoff by device/circuit and architecture Codesign compared to conventional design2.5 improvement3.8 improvement

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