VLSI Design

VLSI Design / 2009 / Article / Tab 8

Review Article

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Table 8

Sub-CMOS versus Subdomino logic [22].


Power (nw)10.643.408 (32%)
Delay ( s)7.5452.423 (3 faster)
PDP (fJ)80.288.26 (10%)
Area ( m2)23811447 (60%)

Noise marginspoorexcellent

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at help@hindawi.com to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19. Sign up here as a reviewer to help fast-track new submissions.