Review Article
Device and Circuit Design Challenges in the Digital Subthreshold
Region for Ultralow-Power Applications
Table 8
Sub-CMOS versus Subdomino logic [
22].
| | Parameter | Sub-CMOS | Subdomino |
| | Power (nw) | 10.64 | 3.408 (32%) | | Delay (s) | 7.545 | 2.423 (3 faster) | | PDP (fJ) | 80.28 | 8.26 (10%) | | Area (m2) | 2381 | 1447 (60%) |
| | Noise margins | poor | excellent |
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