VLSI Design

VLSI Design / 2009 / Article / Tab 8

Review Article

Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications

Table 8

Sub-CMOS versus Subdomino logic [22].

ParameterSub-CMOSSubdomino

Power (nw)10.643.408 (32%)
Delay ( s)7.5452.423 (3 faster)
PDP (fJ)80.288.26 (10%)
Area ( m2)23811447 (60%)

Noise marginspoorexcellent

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