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VLSI Design
Volume 2009 (2009), Article ID 415646, 10 pages
Research Article

Low-Cost Allocator Implementations for Networks-on-Chip Routers

Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong

Received 24 June 2009; Revised 18 October 2009; Accepted 19 December 2009

Academic Editor: Maurizio Palesi

Copyright © 2009 Min Zhang and Chiu-Sing Choy. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Cost-effective Networks-on-Chip (NoCs) routers are important for future SoCs and embedded devices. Implementation results show that the generic virtual channel allocator (VA) and the generic switch allocator (SA) of a router consume large amount of area and power. In this paper, after a careful study of the working principle of a VA and the utilization statistics of its arbiters, opportunities to simplify the generic VA are identified. Then, the deadlock problem for a combined switch and virtual channel allocator (SVA) is studied. Next, the impact of the VA simplification on the router critical paths is analyzed. Finally, the generic architecture and two low-cost architectures proposed (the look-ahead, and the SVA) are evaluated with a cycle-accurate network simulator and detailed VLSI implementations. Results show that both the look-ahead and the SVA significantly reduce area and power compared to the generic architecture. Furthermore, cost savings are achieved without performance penalty.