A Multilevel Congestion-Based Global Router

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="537341.fig.004a" src="https://static.hindawi.com/articles/vlsi/volume-2009/537341/figures/537341.fig.004a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>Predicted congestion</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="537341.fig.004b" src="https://static.hindawi.com/articles/vlsi/volume-2009/537341/figures/537341.fig.004b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>Final solution congestion</td></tr></table></td></tr></table>

<table>A predicted congestion map and the actual congestion after routing for the horizontal edges in ibm06. Shading indicates edge demands.</table>

VLSI Design

A Multilevel Congestion-Based Global Router

Figure 4