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VLSI Design
Volume 2009 (2009), Article ID 679853, 7 pages
http://dx.doi.org/10.1155/2009/679853
Research Article

Reduced Voltage Scaling in Clock Distribution Networks

Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX 78249, USA

Received 28 April 2009; Accepted 18 December 2009

Academic Editor: Xianlong Long Hong

Copyright © 2009 Khader Mohammad et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • Khader Mohammad, Ahsan Kabeer, and Tarek Taha, “On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding,” VLSI Design, vol. 2014, pp. 1–14, 2014. View at Publisher ยท View at Google Scholar