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VLSI Design
/
2009
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Article
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Tab 1
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Research Article
Reduced Voltage Scaling in Clock Distribution Networks
Table 1
Comparison of full swing and RVS inverters.
FVS
RVS
Power (uW)
0.279
0.107
Delay (ps)
0.449
0.394
Rise Slew Rate (ps)
0.074
0.168
Fall Slew Rate (ps)
0.074
0.131