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VLSI Design
/
2009
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Article
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Tab 1
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Research Article
Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS
Table 1
Transistor widths in the simulated circuitry.
W
in nm
1-stacked
2-stacked
3-stacked
n
-channel
280
560
840
p
-channel
560
1120
1680